// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 .
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : harness.sv
// Author        : 
// Created On    : 2022-08-25 18:08
// Last Modified : 
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

`ifndef __HARNESS_SV__
`define __HARNESS_SV__

import uvm_pkg::*;

`timescale 1ns/1ps

module harness;

logic clk;
logic rst_n;

initial begin
   clk = 0;
   forever begin
      #10 clk = ~clk;
   end
end

initial begin
   rst_n = 1'b0;
   #100;
   rst_n = 1'b1;
end

initial begin
   run_test("sanity_case");
end

gjm_interface u_if(clk, rst_n);

initial begin
   uvm_config_db#(virtual gjm_interface)::set(null, "uvm_test_top.env.agt", "vif", u_if);
end

endmodule

`endif
